1. Field of the Invention
The present invention generally relates to an image processing device which is applied to a scanner, a facsimile machine, a copier and so forth, and, in particular, to a high-speed image processing technique.
2. Description of the Prior Art
Recently, the image data processing speed has been increased in a digital copier, a scanner and so forth. In order to achieve high-speed image data processing, it is necessary that an original image is rapidly read, and image processing is performed on thus-obtained image data at high speed. However, when the frequency of the pixel clock is increased, reliability may decrease due to heat generated in circuits, and/or lack of operation margin. Further, trouble due to radio wave may occur.
Therefore, a method for increasing the image data processing speed without increasing the frequency of the pixel clock has been devised. For example, Japanese Laid-Open patent application Ser. No. 6-98165 discloses a technique in which one page of image data is divided in the main scan direction into a plurality of blocks, the blocks of image data are processed in parallel, and the image data which is once divided to the blocks is returned to line units, so that image data processing for a plurality of blocks is performed easily.
In the above-described prior art, a line is divided into blocks, and the respective blocks of image data are processed using the same synchronization signal. Accordingly, it is not possible to perform a plurality of types of image processing in a condition in which each type of image processing is performed in parallel.
In the specification and claims of the present application, each of the terms xe2x80x98linexe2x80x99, xe2x80x98line of dataxe2x80x99 and xe2x80x98line of image dataxe2x80x99 means a series of image data corresponding to a row of pixels arranged in the main scan direction, a page of image being obtained as a result of a plurality of rows of pixels being arranged in the sub-scan direction.
An object of the present invention is to provide an image processing device which can perform a plurality of types of image processing at high speed.
In order to achieve this object, an image processing device, according to the present invention, which receives image data from an image reading device which divides each line of image data into xe2x80x98nxe2x80x99 blocks of image data, the xe2x80x98nxe2x80x99 being an arbitrary number, and transfers the xe2x80x98nxe2x80x99 blocks of image data in synchronization with respective synchronization signals, and performs predetermined image processing on the image data received from the image reading device, comprises:
a first image processing portion which, using respective synchronization signals for the xe2x80x98nxe2x80x99 blocks of image data, performs first predetermined image processing on the image data in parallel; and
a second image processing portion which combines the xe2x80x98nxe2x80x99 blocks of image data in line units, and performs second predetermined image processing on the image data in parallel using synchronization signals, the period of each of which is xe2x80x98nxe2x80x99 times the period of each of the respective synchronization signals used by the first image processing portion.
In this arrangement, first, using the respective synchronization signals for the xe2x80x98nxe2x80x99 blocks of image data, the first predetermined image processing is performed on the image data in parallel. Then, the xe2x80x98nxe2x80x99 blocks of image data are combined in line units, and the second predetermined image processing is performed on the thus-obtained image data in parallel using the synchronization signals, the period of each of which is xe2x80x98nxe2x80x99 times the period of each of the respective synchronization signals used by the first image processing portion. This enables parallel processing suitable for each image processing, and, as a result, it is possible to achieve high-speed image processing.
The image processing device may further comprise:
a third image processing portion which again divides each line of image data into xe2x80x98nxe2x80x99 blocks of image data, and performs third predetermined image processing on the thus-obtained image data in parallel using respective synchronization signals, the period of each of which is the original period; and
a line-data obtaining portion which converts the xe2x80x98nxe2x80x99 blocks of image data output from the third image processing portion into parallel data so as to reduce the period of each of the respective synchronization signals for the xe2x80x98nxe2x80x99 blocks of image data so that the period becomes 1/n times the original one, and, also, to decrease the frequency of a pixel clock, thus the xe2x80x98nxe2x80x99 blocks of image data being transferred in synchronization with the respective synchronization signals, the period of each of which is 1/n times the original one, then combines the xe2x80x98nxe2x80x99 blocks of image data, and, thus, obtains each line of image data which is transferred in synchronization with a synchronization signal, the period of which is the original one, and in synchronization with the pixel clock, the frequency of which is reduced.
In this arrangement, each line of image data is again divided into xe2x80x98nxe2x80x99 blocks of image data, and the third predetermined image processing is performed on the thus-obtained image data in parallel using the respective synchronization signals, the period of each of which is the original period. Then, the xe2x80x98nxe2x80x99 blocks of image data are converted into parallel data so as to decrease the period of each of the respective synchronization signals of the xe2x80x98nxe2x80x99 blocks of image data to be 1/n times the original one, and, also, to reduce the frequency of the pixel clock, the xe2x80x98nxe2x80x99 blocks of image data being thus transferred in synchronization with the respective synchronization signals, the period of each of which is 1/n times the above-mentioned original one, then, the xe2x80x98nxe2x80x99 blocks of image data are combined, and, thus, each line of image data is obtained, which is transferred in synchronization with the synchronization signal, the period of which is the above-mentioned original one, and in synchronization with the pixel clock, the frequency of which is reduced. Thereby, when the thus-obtained image data is transferred to a subsequent stage, the subsequent stage can perform one-line processing without considering the block division. As a result, the control becomes easier. Further, as a result of the frequency of the pixel clock being decreased, a possibility that problematic radiation noise develops is reduced.
An image processing device, according to another aspect of the present invention, which receives image data from an image reading device which divides each line of image data into xe2x80x98nxe2x80x99 blocks of image data, the xe2x80x98nxe2x80x99 being an arbitrary number, and transfers the xe2x80x98nxe2x80x99 blocks of image data in synchronization with respective synchronization signals, comprises:
an image processing portion which performs predetermined image processing on the image data, and comprises a first processing portion which, using respective synchronization signals for the xe2x80x98nxe2x80x99 blocks of image data, performs first predetermined image processing on the image data in parallel, and a second processing portion which combines the xe2x80x98nxe2x80x99 blocks of image data in line units, and performs second predetermined image processing on the image data in parallel using synchronization signals, the period of each of which is xe2x80x98nxe2x80x99 times the period of each of the respective synchronization signals; and
an image-combination processing portion which performs processing of combining image data produced by an image producing portion and the image data output from the image processing portion.
Thereby, it is possible to combine the image data, registered in the image producing portion, with the image data, obtained as a result of each line being divided into xe2x80x98nxe2x80x99 blocks, at an arbitrary position of the image.
The image processing portion may further comprises a third processing portion which again divides each line of image data into xe2x80x98nxe2x80x99 blocks of image data, and performs third predetermined image processing on the thus-obtained image data in parallel using respective synchronization signals, the period of each of which is the original period; and the image-combination processing portion may perform the processing of combining the image data produced by the image producing portion and the image data which is obtained as a result of the xe2x80x98nxe2x80x99 blocks of image data output from the third processing portion of the image processing portion being converted into parallel data so as to reduce the period of each of the respective synchronization signals of the xe2x80x98nxe2x80x99 blocks of image data to 1/n times the original one, and, also, to reduce the frequency of a pixel clock, the xe2x80x98nxe2x80x99 blocks of image data being thus in synchronization with the respective synchronization signals, the period of each of which is 1/n times the original one, the xe2x80x98nxe2x80x99 blocks of image data being then combined, and each line of image data being obtained, which is in synchronization with a synchronization signal, the period of which is the original one, and in synchronization with the pixel clock, the frequency of which is reduced.
In this arrangement, only the single image producing portion is needed. As a result, it is possible to lower the costs.
The image processing device may further comprise an input interface for inputting image data to the image producing portion. Thereby, it is possible to register an arbitrary image data in the image producing portion in arbitrary timing, and perform image combination using the thus-registered image data.
A single data bus may be used for inputting the image data to the image producing portion, and, also, for outputting the image data from the image producing portion. Thereby, when the image producing portion and the image processing device including all the portions other than the image producing portion are included in separate circuit blocks, respectively, it is possible to reduce the number of wiring members between these two circuit blocks. As a result, it is possible to lower the costs.